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ADV7195
Table II must be followed when programming the control sig-
nals in Async Timing Mode.
Table II. Truth Table
SYNC
TSYNC
DV
1 –> 0
0
0 or 1
50% Point of Falling Edge of
Tri-Level Horizontal Sync
Signal, A
0
0 –> 1
0 or 1
25% Point of Rising Edge of
Tri-Level Horizontal Sync
Signal, B
0 –> 1
0 or 1
0
50% Point of Falling Edge of
Tri-Level Horizontal Sync
Signal, C
1
1
0 or 1
0 or 1
0 –> 1
1 –> 0
50% Start of Active Video, D
50% End of Active Video, E
CLK
SYNC
TSYNC
DV
SET MR06 = 1
PROGRAMMABLE
INPUT TIMING
HORIZONTAL SYNC
ACTIVE VIDEO
ANALOG
OUTPUT
81
A
66
B
66
C
243
D
1920
E
Figure 17. Async Timing Mode—Programming Input Control Signals for SMPTE295M Compatibility
VIDEO
525
1
12
13
42
43
OUTPUT
HSYNC
VSYNC
DV
Figure 18. DV Input Control Signal in Relation to Video Output Signal
REV. A
–15 –
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